This invention relates to a phase detector circuit, and in particular to a phase detector which can be used in a phase locked loop. More specifically, the invention relates to a phase detector which triggers on both edges of a system clock, thus effectively doubling the reference frequency without adding circuitry and noise.
In digital communication systems, for example in mobile telephone communications operating under the GSM or DCS systems, a technique of continuous phase modulation (CPM) is used.
Phase locked loops are well known. A signal at a reference frequency provides an input to a phase detector, the output of which is filtered and passed to a voltage control oscillator. The output from this voltage control oscillator is the output from the phase locked loop, and is also fed back to a frequency divider. The output from the frequency divider is fed back to the phase detector, and the circuit acts to bring the output of the loop to a frequency which is equal to the reference frequency multiplied by the division ratio of the frequency divider. Frequency or phase modulation is therefore achieved by using an input information-containing signal to control a programmable frequency divider, which is preferably a fractional-N divider, that is, one which can provide non-integer division ratios.
U.S. Pat. No. 4,814,726 shows a circuit of this type.
In general, in such a circuit, noise signals which appear in the reference signal, or are generated by the phase detector, are amplified by a factor which corresponds to the division ratio of the frequency divider. Therefore, it is advantageous to be able to increase the reference frequency, and hence reduce this division ratio. However, the introduction of, for example, a frequency doubler to increase the reference frequency and reduce the noise contribution, requires the addition of extra circuitry, and increases the size and current consumption of the circuit.